Network computing is the execution of various applications at servers, routers and end points in the Internet by processing packets on the fly. Unlike scientific computing, it is characterized by a request arrival process at the server, intermittent service demands, customized computations, and departures. The applications include web service, data center workloads, content aware routing, deep packet inspection (DPI), and multimedia, etc. The processing can be computationally expensive that adds delays, reduces throughput, and degrades the quality of service (QoS) of the requests. This talk presents scheduling techniques that can be adopted to save power and energy consumption when the network traffic is low.
Our research over the years has developed techniques to tackle the problems of packet processing by designing efficient scheduling techniques for multicore architectures. By exploiting locality and load balancing at the same time, we have developed and tested different algorithms on commercial platforms for many applications. In addition to presenting brief results on scheduling, this presentation will focus on different techniques to save energy in a multicore server. We develop suitable load distribution of incoming packets to multiple cores in the server, and apply DVFS and clock gating power saving techniques. Our research also develops vacation and rate adaptation schemes and saves power by driving the CPU cores to deep sleep states while satisfying the latency and QoS constraints. Both static and runtime techniques are designed, implemented, and evaluated using commercial multicore processors. Some measurement results are presented.

Laxmi Narayan Bhuyan is Distinguished Professor of Computer Science and Engineering Department at the University of California, Riverside (UCR). Prior to joining UCR in January 2001, he was a professor of Computer Science at Texas A&M University (1989-2000) and Program Director of the Computer System Architecture Program at the National Science Foundation (1998-2000). He has also worked as a consultant to Intel and HP Labs.

Dr. Bhuyan received his Ph.D. degree in Computer Engineering from Wayne State University in 1982. His current research interests are in the areas of network packet processing, multiprocessor architectures, network processors and I/O architectures, high-performance IP routers, parallel and distributed processing, and performance evaluation. He has published more than 150 papers in these areas in IEEE Transactions on Computers (TC), IEEE Transactions on Parallel and Distributed Systems (TPDS), Journal of Parallel and Distributed Computing (JPDC), and many refereed conference proceedings.

Dr. Bhuyan served as the Editor-in-Chief of the IEEE Transactions on Parallel and Distributed Systems (TPDS) from 2006 to 2009. He is a past Editor of the IEEE TC, JPDC, and Parallel Computing Journal. His professional activities are too numerous to describe. To mention a few, he was the founding Program Committee Chairman of the HPCA in 1995, Program Chair of the IPDPS in 1996, General Chair of ADCOM-2001, and General Chair of HPCA-9 (2003). He was elected Chair of the IEEE Computer Society Technical Committee on Computer Architecture (TCCA) between 1995-1998. He is also a Fulbright Senior Specialist.

Dr. Bhuyan is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the AAAS (American Association for the Advancement of Science), and a Fellow of the WIF (World Innovation Foundation). He has also been named as an ISI Highly Cited Researcher in Computer Science. He has received other awards such as Halliburton Professorship at Texas A&M University, and Senior Fellow of the Texas Engineering Experiment Station. He was also awarded the IEEE CS Outstanding Contribution Award in 1997. He was inducted into the Distinguished Alumni Hall of Fame of the Wayne State University College of Engineering in October 2010. He received the Distinguished Alumnus Award from National Institute of Technology, Rourkela in 2011.